FIG. 1 illustrates a prior art logarithmic amplifier (log amp) that utilizes the logarithmic properties of a bipolar junction transistor (BJT) to measure a signal having a large dynamic range. The operational amplifier (op amp) OA1 forces the collector current IC of transistor Q1 to equal the input current IX while maintaining the collector-base voltage very close to zero. The output signal VLOG is then equal to the base-emitter voltage of transistor Q1. Because the output has a logarithmic relation to the input as explained below, the large dynamic range of the input signal is reduced to relatively smaller dynamic range at the output for ease of further processing.
The circuit of FIG. 1, which is known as a transdiode connection or Patterson diode, takes advantage of the very reliable mathematical relationship between the collector current (IC) and the base-emitter voltage (VBE) which may be expressed as follows:VBE=VK ln(IC/IS+1)  (Eq. 1)where VK is the thermal voltage kT/q which is about 26 mV at 300° K, and IS is commonly called the “saturation current” which is a basic scaling parameter for a BJT. (The thermal voltage has traditionally been indicated by VT in the literature, but the use of VK is generally being adopted to distinguish from the threshold voltage VT of a field-effect transistor.) In most practical situations, IC>>IS, so Equation 1 may be simplified by eliminating the +1 term from the argument of the ln function as follows:VBE≠VK ln(IC/IS)  (Eq. 2)The approximation of Equation 2 is generally valid for most operating conditions except at very low currents and high temperatures as described in more detail below. Therefore, Equation 2 and other mathematical relationships related to it may be written herein with an equal sign with the understanding that it is an approximation that is valid under most conditions.
Base-10 logarithms are commonly used to characterize the output of a log amp directly in terms of decibel (dB) changes in the input signal. It is also common to characterize the operation of a log amp in terms of a “slope voltage,” defined as the amount of change in the output for each decade change in the input magnitude, and an “intercept,” which is the value of input at which the extrapolation of the output in Equation 2 passes through zero. Therefore, using the expression VY=VK ln(10) and substituting IX for IC and VLOG for VBE, Equation 2 may be rearranged as follows:VLOG=VY log10(IX/IZ)  (Eq. 3)where VLOG is the output voltage, IX is the input current, VY is the slope voltage, and IZ is the intercept. From Equations 2 and 3, it is apparent that the log amp of FIG. 1 has a slope voltage VY of −VK and an intercept IZ of IS.
At any given calibration temperature, the circuit of FIG. 1 can provide a remarkably accurate measure of the logarithm of a fixed-polarity, constant or varying input current, and the op amp OA1 allows the output to be loaded while preserving accuracy. However, the saturation current IS is an extremely strong function of temperature, while the thermal voltage VK is proportional to absolute temperature (PTAT). Accordingly, further refinements are needed to ensure the calibration is essentially independent of temperature.
FIG. 2 illustrates a prior art elaboration of the Paterson diode connection providing a stable log-intercept through elimination of the temperature dependence of IS. This scheme uses a second transistor Q2, nominally identical to Q1, and a second op amp OA2 configured as a unity-gain buffer (voltage follower) with its output fed back to its inverting (−) input terminal. With this topology, the output is the difference of the two base-emitter voltages:
                              V          LOG                =                                            -                              V                K                                      ⁢                          log              ⁡                              (                                                      I                    Z                                    /                                      I                    S                                                  )                                              +                                    V              K                        ⁢                          log              ⁡                              (                                                      I                    X                                    /                                      I                    S                                                  )                                                                                                  ⁢                  (                                    Eq              .                                                          ⁢              4                        ⁢            a                    )                                        =                              V            K                    ⁢                      log            (                                          I                X                            /                              I                Z                                      )                                                                        ⁢                  (                                    Eq              .                                                          ⁢              4                        ⁢            b                    )                                        =                              V            Y                    ⁢                                    log              10                        ⁡                          (                                                I                  X                                /                                  I                  Z                                            )                                                                                    ⁢                  (                                    Eq              .                                                          ⁢              4                        ⁢            c                    )                    where the inputs have been swapped to make VLOG turn out positive. Therefore, the uncertain value of IS has been eliminated, and the intercept is now determined by the reference current IZ which, using well-known techniques, can be supplied by an accurate and temperature-stable current source. This scheme offers “log-ratio” operation.
The logarithmic output VLOG still has a temperature-dependent slope VK=kT/q, alternatively written VY=(kT/q)log(10). Temperature compensation of the slope is typically achieved through the use of an analog multiplier as shown in FIG. 3. A translinear multiplier cell 10 is used to form the feedback loop with the logging transistors Q1 and Q2. The temperature compensation of the slope is achieved by using a PTAT current It, and a temperature-stable current Ir for biasing the two halves of the multiplier cell. This circuit and further refinements are described more fully in U.S. Pat. No. 4,604,532, by the same inventor as the present patent disclosure.
FIG. 4 illustrates another prior art logarithmic circuit that operates on the same fundamental principles as the Patterson diode, but with the emitter of the log transistor referenced to a ground node. The base of Q1, from which the logarithmic output signal VBE is taken, is driven by a differential-input amplifier 14, preferably a high-gain, FET-input operational amplifier (op amp), which has its noninverting (+) input coupled to the collector of Q1 and its inverting (−) input coupled to a voltage VSUM that sets the voltage at the input (“summing”) node.
As with a Patterson diode arrangement, the circuit of FIG. 4 can be combined with a reference cell to form a differential-output, log-ratio circuit, as shown in FIG. 5. The reference cell is implemented with a second log transistor Q2 having its emitter grounded and its collector arranged to receive a second input current I2. A second amplifier 16 has its noninverting (+) input coupled to the collector of Q2 and its inverting (−) input coupled to the same reference voltage VSUM as the first amplifier 14. In this embodiment, amplifiers 14 and 16 are preferably high-gain op amps, and VSUM is typically 0.5 volts. The logarithmic output signal ΔVBE is taken as the difference between the base voltages of Q1 and Q2 and behaves according to the following equation:ΔVBE=VBE1−VBE2=VK log(I1/I2)  (Eq. 5)
If the second input current I2 is stable with temperature, and transistors Q1 and Q2 are isothermal and nominally identical, the circuit of FIG. 5 provides a log amp in which the intercept has been temperature stabilized. That is, the highly temperature and process dependent saturation current IS for Q1 cancels the IS of Q2, so the intercept depends only on the value of I2. The temperature variability in the slope remains, introduced by the thermal voltage VK=kT/q in Equation 5. This remaining temperature-dependency can be eliminated by using a translinear multiplier cell to implement the temperature compensation of the thermal voltage VK in Equation 5, thereby stabilizing the slope. The second input terminal in the circuit of FIG. 5 can also be used to realize log-ratio operation rather than a log amp having a fixed intercept. This circuit and further refinements are described more fully in U.S. Pat. No. 7,310,656 by the same inventor as the present patent disclosure.